VLSI Designs for Joint Channel Estimation and Data Detection in Large SIMO Wireless Systems

摘要

Channel estimation errors have a critical impact on the reliability ofwireless communication systems. While virtually all existing wireless receiversseparate channel estimation from data detection, it is well known that jointchannel estimation and data detection (JED) significantly outperformsconventional methods at the cost of high computational complexity. In thispaper, we propose a novel JED algorithm and corresponding VLSI designs forlarge single-input multiple-output (SIMO) wireless systems that useconstant-modulus constellations. The proposed algorithm is referred to asPRojection Onto conveX hull (PrOX) and relies on biconvex relaxation (BCR),which enables us to efficiently compute an approximate solution of themaximum-likelihood JED problem. Since BCR solves a biconvex problem viaalternating optimization, we provide a theoretical convergence analysis forPrOX. We design a scalable, high-throughput VLSI architecture that uses alinear array of processing elements to minimize hardware complexity. We developcorresponding field-programmable gate array (FPGA) and application-specificintegrated circuit (ASIC) designs, and we demonstrate that PrOX significantlyoutperforms the only other existing JED design in terms of throughput,hardware-efficiency, and energy-efficiency.